Induction alternating-current (AC) motors are advantageous by comparison with direct-current or synchronous motors in that they do not require commutators, contact brushes or slip rings to provide energization to the rotor. The induction motor thus lacks a wear part, and so can be more reliable. The advent of solid-state motor controls has made the AC motor practicable for direct torque control and variable speed servo applications. AC-Link AC-to-AC converter or load controller act as pure current source power supplies, providing superior fast response for current control than does a voltage source.
FIG. 1 is a simplified block diagram illustrating a prior-art load, hardware and controller designated together as 210. In FIG. 1, the load 212 of receives three-phase alternating current by way of a path 213 from a switched hardware arrangement illustrated as a block 214. The three phases of load current appearing at hardware output ports 32 are designated Ia, Ib, and Ic. Switched hardware arrangement 214 receives 3-phase alternating voltage Va, Vb, and Vc at input ports 12 from the power mains, illustrated as 216. Hardware block 214 may include switching elements such as those illustrated in FIG. 2. The hardware circuit of FIG. 2 is described in U.S. Pat. No. 7,659,700, issued Feb. 9, 2010 in the name of Holvek et al. and the type of circuit is described more generally in U.S. Pat. No. 6,118,678, issued Sep. 12, 2000 in the name of Limpaecher et al.
In the prior-art arrangement of FIG. 1, switching control circuit 218 receives command signals from a command control block 220, and translates the command signals into switching control signals for the various switches of FIG. 2. Switching control circuit 218 also receives information (“sensed signals”) relating to the operating parameters of hardware block 214 by way of a set of paths designated 301, 303. As described by Holvek et al., hardware apparatus 10 includes a three-phase “input” terminal 12 defining three input terminals 121, 122, and 123. An input filter inductor section 14 including inductors 141, 142, and 143 is connected between input terminal 12 and an input filter capacitor section 16. Filter capacitor section 16 includes input filter capacitors 161, 162, and 163. A switching section 18 of controllable input controllable unidirectional current conductive devices (switches) is coupled to filter capacitor section 16, and includes switches Si1p, Si1n, Si2p, Si2n, Si3p, and Si3n. Among the switches of section 18, Si1p, Si2p, and Si3p conduct current in a first direction, and have their cathodes connected together at a first node 19a. Controllable switches Si1n, Si2n, and Si3n conduct current in a second or opposite direction, and have their anodes connected to a second node 19b. A “central” capacitor 22 is connected between nodes 19b and 22a. A charging inductor 20 is connected between node 19a and node 22a. A “freewheeling” unidirectional current conducting device in the form of a diode or rectifier 24 has its anode connected to node 22a and its cathode connected to a node 25a. A freewheeling controllable switch 26 has its anode connected to node 19b and its cathode connected to node 25a. A discharge inductor 40 is connected between nodes 25a and 27a. An output switch set 38 includes controllable switches So1p, So2p, So3p, So1n, So2n, and So3n. Output switch set 38 connects nodes 19b and 27a to a set 36 of output filter capacitors 361, 362, and 363, and through a set 34 of output filter inductors 341, 342, and 343 to a three-phase load 212 connected to terminals 321, 322, and 333.
FIG. 3 is a simplified functional block diagram illustrating a prior-art controller 300 for, in “normal” or not-power-limited operating mode, generating the switching control signals for the input and output switch sets 18 and 38 of FIG. 2. All the functions 300 illustrated in FIG. 3 may be performed in a digital processor or a plurality of conjoined digital processors. In FIG. 3, elements corresponding to those of FIGS. 1 and 2 are designated by like alphanumerics. In the prior art arrangement of FIG. 3, controller 300 receives digital signals at an input port 218i1 representing the commanded phase of the IAC-Link (load) current (IAC-Link), and also receives digital signals at input port 218i2 representing the commanded magnitude of the IAC-Link current. The IAC-Link current is the instantaneous three-phase input current to load 212 of FIG. 1. Controller 300 of FIG. 3 also receives digital signals Vin, Iin, Icc, Vcc, Vout, and lout on a bus 301. Vin represents the instantaneous input voltage applied from 3-phase source 216 to hardware 2140f FIG. 1, Iin represents the instantaneous current applied from 3-phase source 216 to hardware 214, Icc represents the instantaneous current flow through the central capacitor 22 of FIG. 2. Vout and Iout also appear on bus 301, and represent the instantaneous output voltage and current of hardware 214 of FIG. 2. In addition, a processing block 302 receives by way of path 303 signals Vct0 and Vct4, which are sensed central capacitor 22 voltage at switching times t0 and t4, respectively. Times t0 and t4 are related to various switching times of the switches of hardware 214. Processing block 302 performs the calculationsq.toA=(Vct4−Vct0)*CC where:                A represents an actual (measured) value;        O represents an output value;        t represents a total value;        q represents charge on the central capacitor;        * represents multiplication; and        CC represents the capacitance of central capacitor 22 of FIG. 2.The q.toA output of block 302 represents the actual output or total discharge on the central capacitor and on the entire hardware. It also represents how much charge should be or has been applied to the motor during the switching event.        
In FIG. 3, a source 304 of digital signals generates [signalq.toI=IOSCR_MAX/PULSE_FREQ_MAXwhere:                IOSCR_MAX is the maximum current that the hardware can carry, and is stored in memory; and        PULSE_FREQ_MAX is maximum switching frequency of the hardware, also stored in memory.Signal q.toI produced by block 304 represent ideal output total capacitor discharge to be applied or transferred to load 212 during the current (contemporaneous) switching event. Signals q.toI are applied from block 304 to a noninverting (+) input port of an error detector or differencing circuit 306. Processing block 302 applies signalq.toa=(Vct4−Vct0)*CC to the inverting (−) input port of error detector 306, where:        Vcct0 is voltage across central capacitor 22 at time t0;        Vcct4 is voltage across central capacitor 22 at time t4. Signal q.toa represents the actual total discharge transferred from the central capacitor during the current switching event. Error detector 306 produces a signal q.toE representing the difference between the actual and ideal capacitor discharge transferred during the current switching event. The q.toE error signal is applied from the output port of error detector 306 to a proportional-integral (PI) controller block 308. The processing in block 308 is given byq.inFactor=Kp*e(t)+Ki*integral(e(t)dt)where:        Kp is the proportional gain; and        Ki is the integral gain, both of which are preset.        
The q.inFactor signal produced by PI controller 308 of FIG. 3 is applied from an output port 308o by way of a bus 309 to timing calculations for the switches of the hardware 10 of FIG. 2. More particularly, the output signal from output port 3080 of block 308 is applied by way of bus 309 to blocks designated generally as 350 for calculation of the timing for the input switches 18 of hardware 10 of FIG. 2. Input switch timing calculations 350 of FIG. 3 include blocks 310, 314, 316, 318, 320, 322, 324, and 326. Decision block 310 of FIG. 3 examines the q.inFactor signal, and determines if the q.inFactor signal is less than zero (<0). If the q.inFactor signal is greater than zero, the logic leaves decision block 310 by the NO (N) output, and arrives at a block 314 of a branch 350a of the input switch timing calculation group 350. Block 314 calculates “inversion negative” target voltage of the central capacitor 22 vTarget as being equal to a function of q.inFactor.vTarget=Vct0+2[Vin−Vct0]The input energy EnergyIn of central capacitor 22 is calculated in block 316 asEnergyIn=½*CC*(vTarget^2*Vcct0^2)where:                Vcct0 is voltage across central capacitor 22 at time t0.From block 316, the logic of FIG. 3 flows to a block 318. Block 318 represents calculation, using a function of Vin and energyin, of q.tsed and q.tter, which are the charge that should be transferred for the first switching event and the charge that should be transferred for the second switching event, respectively. The q.tsec and q.tter signals from block 318 are made available to an input timing calculation block 326.        
As mentioned, decision block 310 of FIG. 3 examines the q.inFactor signal, and determines if the q.inFactor signal is less than zero (<0). If the q.inFactor signal is less than zero, the logic leaves decision block 310 by the YES (Y) output, and arrives at an inversion positive block 320 of a branch 350b of the input switch timing calculation group 350. Block 320 receives a damping factor q.dampFactorQ from a block 322. Block 322 calculates the damping factor as
      q    .    dampFactorQ    =      2    *          (              Vin                  VcinAvg          -          1                    )      where:                Vin is the instantaneous value of voltage at port 12 of the hardware of FIG. 2; and        VCinAvg is the average of the input voltage at port 12 of the hardware 10 of FIG. 2.The qdampFactorQ signal is applied from block 322 to block 320.        
Block 320 receives the qdampFactorQ signal and calculates a signal q.til.adjq.til.adj=q.inFactor*(1+q.dampFactorQ)*q.tol representing the adjustment for the charge need to be transferred for next switching event from last switching event, and applies the signal to a block 324. Block 324 calculates q.tsec* and q.tter*.q.tsec=(q.tll.adj)*q.tsec q.tter=(q.tll.adj)*q.tter where:                q.tsec* is the charge that should be transferred from the central capacitor for the first switching event;        q.tiI.adj is an adjustment to the charge that should ideally be transferred from the central capacitor for the next switching event from the last or previous switching event;        q.tter* is the charge that should be transferred from the central capacitor for the second switching event. The values of q.tsec* and q.tter* are applied from block 324 to block 326. Thus, the q.tsec and q.tter are ultimately applied to input switch timing calculation block 326 regardless of the decision as to the magnitude of the q.inFactor by decision block 310.        
Block 326 of FIG. 3 receives the inversion positive signals q.tsec* and q.tter* from block 324 or the inversion negative signals q.tsec and q.tter from block 318, depending upon the state of decision block 310. Block 326 also receives Vin, Iin, ICC, VCC, Vout, and Iout information from bus 301, where ICC and VCC represent instantaneous measurements of the current and voltage of central capacitor 22, respectively. Block 326 performs various calculations to determine the timing t1 and t2 of the input switches of set 18 of FIG. 2. The timing t1 is calculated with the equations
            V      1        =                  Vct        ⁢                                  ⁢        0            -      Vin                          q        .        t            ⁢                          ⁢      sec        =                  ∫                  t          ⁢                                          ⁢          0                          t          ⁢                                          ⁢          1                    ⁢              cc        *                                  ⁢                  ⅆ          V                ⁢                                  ⁢        1            where:                V1 is the equivalent voltage applied during the interval t0 to t1 to charging inductor 20 of FIG. 2.The timing t2 is calculated with the equations        
            Vct      ⁢                          ⁢      1        =                            q          .          t                ⁢                                  ⁢        sec            cc                  V      ⁢                          ⁢      2        =                  Vct        ⁢                                  ⁢        1            -      Vin                  q      .      tter        =                  ∫                  t          ⁢                                          ⁢          1                          t          ⁢                                          ⁢          2                    ⁢              cc        *                                  ⁢                  ⅆ          V                ⁢                                  ⁢        2            where:                V2 is the equivalent voltage applied during the interval t1 to t2 to charging inductor 20 of FIG. 2. The timing information t1 and t2 is applied to the hardware 214 for controlling the input switches 18.        
A memory 328 stores information about time parameter t4, and provides the parameter to hardware block 214 by way of a path 344.
The timing for the output switches 38 of the hardware 10 of FIG. 2 is generated by portion 352 of the controller arrangement 300 of FIG. 3. Portion 352 of controller arrangement 300 includes blocks 336 and 338.
Block 336 of FIG. 3 receives VCC signal from bus 301, representing an estimate of the total discharge of the central capacitor 22 at the last (previous) switching event. Block 336 processes to produce a q.t0A_est signalq.toa_est=q.toI−(|Vct0|−|Vct4|)*cc, which is a function of signal Vct4, the central capacitor voltage at time t4. The q.t0A signal is applied to a block 338. Block 338 performs output timing calculation to determine or establish time t5
            V      ⁢                          ⁢      5        =          Vcc      -      Vout                  q      .      toa_est        =                            ∫                      t            ⁢                                                  ⁢            4                                t            ⁢                                                  ⁢            5                          ⁢        cc            -                          ⁢                        ⅆ          V                ⁢                                  ⁢        5            where:                V5 is the equivalent voltage applied to the central or discharging inductor (40 of FIG. 2).The calculated value of time t5 is applied to hardware 214.        
A further block 340 of FIG. 3 receives IAC-Link from input port 218i2, and calculates the switching timing t0, which is dependent upon the switching frequency.t0=IAC-LINK/q.toi where q.toi is produced by block 304. The calculated switching frequency t0 is applied from block 340 to hardware 214.